It is sometimes desirable to be able to form electrical connections through a chip to facilitate connecting it to another element in an efficient manner. In many cases, this means use of vias and involve connections that are made near the devices of chips as opposed to forming connections at or near the periphery of the chip, as is done with conventional methods.
One drawback to using through-chip vias on fully processed (i.e. device-bearing) chips is that fully formed chips are significantly more expensive than the cost of a comparable piece of blank wafer or a partially processed chip. If an error is made in aligning where the via for the electrical connection will be, a device on the chip or one or more of the metallization layers may be damaged or the desired connection may not be made.
In either case, the result could be a useless chip, requiring scrapping of the chip.